Patent References 3402081 3879746 Fabrication method for integrated circuits with polysilicon lines having low sheet resistance MIS Device having a metal and insulating layer containing at least one cation-trapping element Heterojunction type semiconductor photoelectric conversion device PN Or PIN junction type semiconductor photoelectric conversion device Manufacturing TaSi-polysilicon conductors having high-resistance elements by a liftoff technique Photovoltaic cell Patent #: 4485265 InventorsAssigneeApplicationNo. 06/472517 filed on 03/07/1983US Classes:438/586, Combined with formation of ohmic contact to semiconductor region257/412, Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal)257/754, At least one layer of silicide or polycrystalline silicon257/764, Alloy containing molybdenum, titanium, or tungsten257/E21.292, Inorganic layer composed of nitride (EPO)257/E21.295, Deposition of layer comprising metal, e.g., metal, alloys, metal compounds (EPO)257/E23.163, Principal metal being refractory metal (EPO)257/E29.155, Multiple silicon layers257/E29.16, Gate conductor material being compound or alloy material (e.g., organic material, TiN, MoSi 2 ) (EPO)438/592, Possessing plural conductive layers (e.g., polycide)438/656, Having refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/680, Utilizing chemical vapor deposition (i.e., CVD)438/685, Refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)438/971STOICHIOMETRIC CONTROL OF HOST SUBSTRATE COMPOSITIONExaminersPrimary: Saba, William G.Attorney, Agent or FirmInternational ClassesH01L 21/02 (20060101)H01L 29/40 (20060101) H01L 29/49 (20060101) H01L 21/3205 (20060101) H01L 23/52 (20060101) H01L 21/318 (20060101) H01L 23/532 (20060101) AbstractAn MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.Other References
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