Memory pack addressing system
Patent 4566082 Issued on January 21, 1986. Estimated Expiration Date: 
March 23, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 23, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSpeedup addressing device by detecting repetitive addressing Patent #: 4156290 InventorAssigneeApplicationNo. 06/478181 filed on 03/23/1983US Classes:365/230.03, Plural blocks or banks365/63INTERCONNECTION ARRANGEMENTSExaminersPrimary: Popek, Joseph A.Attorney, Agent or FirmInternational ClassesG06F 12/06 (20060101)G11C 8/12 (20060101) G11C 8/00 (20060101) AbstractDisclosed herein is a system for addressing a memory pack having a plurality of memory chips such as RAMs or ROMs. Each memory chip receives address signals and a chip enable signal. A chip selector generates the chip enable signal in response to a feedback signal from the memory pack provided in response to the memory address lines. Since each memory pack excludes the chip selector circuitry, the memory packs can be made smaller in size. The memory packs are in effect self-configuring since they control the feedback of the address signals to the chip selector which generates the chip enable signals. Many types and capacities of memory packs can be mixed in the system since the pack determines the memory address space in which it resides.Field of SearchUsing selective matrix | |
