Power line carrier FSK data system
March 16, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3900842 3902013 3908115 3909618 Method for remote control through a power supply system and apparatus for carrying out the same Data recovery system resistant to frequency deviations Demodulator for frequency-keyed communication system Current carrier communication system Control system employing a programmable multiple channel controller for transmitting control signals over electrical power lines Automatic remote meter reading and control system InventorAssigneeApplicationNo. 06/475802 filed on 03/16/1983US Classes:375/272, Frequency shift keying329/300, FREQUENCY SHIFT KEYING OR MINIMUM SHIFT KEYING DEMODULATOR340/310.12, Modulation technique375/303, Frequency shift keying375/327, Phase locked loop375/334Frequency shift keyingExaminersPrimary: Ng, Jin F.Assistant: Kuntz, Curtis Attorney, Agent or FirmInternational ClassesH04B 3/54 (20060101)H04L 27/10 (20060101) AbstractA frequency shift keyed (FSK) data transmission system utilizes existing power lines to transmit data by superimposing a high frequency FSK signal on the power line carrier. A transmitter includes a phase locked loop which is locked on the power line carrier frequency and which synthesizes the FSK signal and a timing signal which defines the data rate of the transmitter. As each bit is transmitted, an oscillator control signal either speeds up or slows down the loop oscillator temporarily to produce the FSK signal. A receiver demodulates the data transmission from the power line by separating a power line carrier frequency component and a FSK signal component. The receiver includes a phase locked loop which locks onto the power line carrier frequency and which synthesizes a reference frequency and a timing signal which defines the data rate of the receiver. The receiver also includes a frequency discriminator circuit which compares the FSK signal with the synthesized reference signal and produces a digital data output signal at the data rate synthesized by the phase locked loop. | |
