Method of making submicron FET structure
Patent 4546535 Issued on October 15, 1985. Estimated Expiration Date: 
December 12, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 12, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3460007 3484313 3600651 3664896 Integrated injection logic using oxide isolation Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching Method for forming diffusions having narrow dimensions utilizing reactive ion etching Method for forming an insulator between layers of conductive material High performance bipolar device and method for making same Method for forming a narrow dimensioned region on a body InventorApplicationNo. 06/560624 filed on 12/12/1983US Classes:438/304, Conductive sidewall component257/327, Short channel insulated gate field effect transistor257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/382, With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)257/385, Multiple polysilicon layers257/E21.432, With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO)257/E21.575, Interconnections, comprising conductors and dielectrics, for carrying current between separate components within device (EPO)257/E23.164, Containing semiconductor material, e.g., polysilicon (EPO)257/E29.146, On silicon (EPO)257/E29.155, Multiple silicon layers257/E29.156, Including silicide layer contacting silicon layer (EPO)438/305, Plural doping steps438/307Using same conductivity-type dopantExaminersPrimary: Ozaki, George T.Attorney, Agent or FirmInternational ClassesH01L 21/02 (20060101)H01L 21/336 (20060101) H01L 21/768 (20060101) H01L 29/40 (20060101) H01L 29/49 (20060101) H01L 29/45 (20060101) H01L 21/70 (20060101) H01L 23/52 (20060101) H01L 23/532 (20060101) AbstractA semiconductor body having at least a surface region of a first conductivity is provided with a insulating layer over the surface region. A substantially horizontal first conductive layer is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source, drain and gate region of the device is desired to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped of a second conductivity conductive layer is formed over the openings having these vertical surfaces and over the insulating and conductive layers. The conformal layer is anisotropically etched to substantially remove the horizontal portions of the conformal layer while leaving the openings with a substantially vertical conformal conductive layer on the sides thereof. The body is heated to cause the dopant of a second conductivity to diffuse into the body from the conformal layer to form the source and drain regions and a first insulating layer upon the surface of the first conductive layer and the conformal layer. A second insulating layer is formed over the vertical conformal layer. Then a gate dielectric is formed upon the surface of the semiconductor body between the source and drain regions. Electrical contacts are made to the first conductive layer through the first insulator layer which effectively makes electrical contact to the source and drain regions through the horizontal conductive layer and the vertical conformal conductive layer.Other References
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