High speed buffer memory system with word prefetch
Cache memory organization utilizing miss information holding registers to prevent lockup from cache misses
Data processing system programmable pre-read capability
Method and apparatus for managing data movements from a backing store to a caching buffer store Patent #: 4429363
ApplicationNo. 06/441901 filed on 11/15/1982
ExaminersPrimary: Smith, Jerry
Assistant: Fleming, Michael R.
Attorney, Agent or Firm
International ClassesG06F 12/08 (20060101)
G11B 20/18 (20060101)
AbstractA method for detection of a sequential data stream which can be performed in a data storge subsystem without host computer intervention is disclosed featuring examination of the channel program processed during a read operation for signals indicative that the data is not part of a sequential data stream, for example, embedded seek instructions. If a particular channel program for does not contain such indications, the successive record or records may then be staged to a faster access memory device such as a solid-state cache. The invention is described in a plug-compatible, software-transparent configuration.