Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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US Patent 4535426 - Semiconductor memory device
Estimated Patent Expiration Date:
June 14, 2003Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA memory device of the invention has a P type substrate, a first drain area of N type formed in the substrate, a second drain area of N type formed in the substrate close to the first drain area, and a source area of N+ type formed around the first and second drain areas so that the source area continuously surrounds the drain areas from three sides, e.g., the right, left and top sides of these areas. The combination of the closed arrangement of the drain areas and the surrounding arrangement of the source area decreases minority carriers generated around the drain areas and prevents unbalanced carrier absorption of the drain areas, thereby suppressing the occurrence of a soft error.Other References
| InventorsAssigneeApplicationNo. 06/504157 filed on 06/14/1983US Classes:365/182, Insulated gate devices257/297, With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)257/387, Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E27.101, Load element being a resistor (EPO)365/154Flip-flop (electrical)Field of Search365/182, Insulated gate devices365/174, Semiconductive365/154Flip-flop (electrical)ExaminersPrimary: Fears, Terrell W.Attorney, Agent or FirmUS Patent References4480319Emitter coupled flip flop memory with complementary bipolar loadsIssued on: 10/30/1984 Inventor: Hotta , et al. International ClassH01L 27/11 (20060101)Foreign Application Priority Data1982-07-19 JP |
