Patent ReferencesEmitter coupled flip flop memory with complementary bipolar loads Patent #: 4480319 InventorsAssigneeApplicationNo. 06/504157 filed on 06/14/1983US Classes:365/182, Insulated gate devices257/297, With means for preventing charge leakage due to minority carrier generation (e.g., alpha generated soft error protection or "dark current" leakage protection)257/387, Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate)257/903, FET CONFIGURATION ADAPTED FOR USE AS STATIC MEMORY CELL257/E27.101, Load element being a resistor (EPO)365/154Flip-flop (electrical)ExaminersPrimary: Fears, Terrell W.Attorney, Agent or FirmInternational ClassH01L 27/11 (20060101)Foreign Application Priority Data1982-07-19 JPAbstractA memory device of the invention has a P type substrate, a first drain area of N type formed in the substrate, a second drain area of N type formed in the substrate close to the first drain area, and a source area of N+ type formed around the first and second drain areas so that the source area continuously surrounds the drain areas from three sides, e.g., the right, left and top sides of these areas. The combination of the closed arrangement of the drain areas and the surrounding arrangement of the source area decreases minority carriers generated around the drain areas and prevents unbalanced carrier absorption of the drain areas, thereby suppressing the occurrence of a soft error.Other References
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