Patent ReferencesMicroprocessor chip register bus structure Apparatus and method for switching of data Apparatus for distinguishing heading information from other information in an information processing system Information transferring apparatus Information transfer control system Bidirectional interface utilizing read-only memory, decoder and multiplexer Data interface apparatus for multiple sequential processors Multi-task digital processor employing a priority Address management system Multiple microprocessor intercommunication arrangement Patent #: 4164787 InventorAssigneeApplicationNo. 06/389823 filed on 06/18/1982US Classes:710/39Access request queuingExaminersPrimary: Thomas, James D.Assistant: Eng, David Y. Attorney, Agent or FirmInternational ClassesG06F 7/78 (20060101)G06F 15/16 (20060101) G06F 15/167 (20060101) G06F 7/76 (20060101) AbstractApparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also permits commands and data to be chained in the same queue. The apparatus permits multiple devices to be handled simultaneously. By monitoring the memory address which is being accessed by the minicomputer, the information retrieved from the memory by the microprocessor is selectively validated or invalidated. | |