U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Circular-queue structure

Patent 4535420 Issued on August 13, 1985. Estimated Expiration Date: Icon_subject August 13, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Microprocessor chip register bus structure
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Apparatus and method for switching of data
Patent #: 4032899
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Apparatus for distinguishing heading information from other information in an information processing system
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Patent #: 4115868
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Information transfer control system
Patent #: 4125870
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Inventor: Suzuki ,   et al.

Bidirectional interface utilizing read-only memory, decoder and multiplexer
Patent #: 4127896
Issued on: 11/28/1978
Inventor: Raslavsky, III

Data interface apparatus for multiple sequential processors
Patent #: 4149242
Issued on: 04/10/1979
Inventor: Pirz

Multi-task digital processor employing a priority
Patent #: 4152761
Issued on: 05/01/1979
Inventor: Louie

Address management system
Patent #: 4163280
Issued on: 07/31/1979
Inventor: Mori ,   et al.

Multiple microprocessor intercommunication arrangement Patent #: 4164787
Issued on: 08/14/1979
Inventor: Aranguren

Inventor

Assignee

Application

No. 06/389823 filed on 06/18/1982

US Classes:

710/39Access request queuing

Examiners

Primary: Thomas, James D.
Assistant: Eng, David Y.

Attorney, Agent or Firm

International Classes

G06F 7/78 (20060101)
G06F 15/16 (20060101)
G06F 15/167 (20060101)
G06F 7/76 (20060101)

Abstract

Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also permits commands and data to be chained in the same queue. The apparatus permits multiple devices to be handled simultaneously. By monitoring the memory address which is being accessed by the minicomputer, the information retrieved from the memory by the microprocessor is selectively validated or invalidated.

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