ROM security circuit
Patent 4513389 Issued on April 23, 1985. Estimated Expiration Date: 
April 23, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 23, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3736569 Data processing system Microword address branching bit arrangement Calculator program security system ROM Program security circuits Memory protection system Memory security circuit using the simultaneous occurance of two signals to enable the memory Patent #: 4384326 InventorAssigneeApplicationNo. 06/320790 filed on 11/12/1981US Classes:711/164, With password or key713/340Having power source monitoringExaminersPrimary: Chan, Eddie P.Assistant: Dorsey, Dennis L. Attorney, Agent or FirmInternational ClassG06F 12/14 (20060101)AbstractA control circuit to disable the operation of a semiconductor microprocessor memory device in the event of an unauthorized attempt to access the memory. A logic circuit generates a control signal in response to receiving a predetermined binary bit pattern of a plurality of chip select signals. The control signal enables the memory device for operation. If the binary bit pattern is not presented, the memory device is disabled for operation. | |
