Peripheral interface adapter circuit for use in I/O controller card having multiple modes of operation
April 2, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3673576 Circuit arrangement for selecting the function of connection contacts on circuit chips Integrated circuit data handling apparatus for a data processing system, having a plurality of modes of operation Request forwarding system Port select unit for a programmable serial-bit microprocessor Interface adaptor architecture Data processor input/output controller Direct memory access control system with byte/word control of data bus Apparatus enabling the transfer of data blocks of variable lengths between two memory interfaces of different widths Reconfigurable register and logic circuitry device for selective connection to external buses InventorApplicationNo. 06/345177 filed on 02/02/1982US Classes:710/66, Width conversion703/25, I/O adapter (e.g., port, controller)703/27Compatibility emulationExaminersPrimary: Zache, Raulfe B.Attorney, Agent or FirmInternational ClassesG06F 13/42 (20060101)G06F 13/12 (20060101) G06F 13/38 (20060101) G06F 13/40 (20060101) AbstractThis adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently. In one handshaking mode, the adapter sustains an array indexing operation in which one section transfers "address" data to a device and the other section transfers "addressed" portions of a data array between the same device and either the host processor or the microprocessor.Other References
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