Method of fabricating power MOSFET structure utilizing self-aligned diffusion and etching techniques
May 20, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of making metal oxide semiconductor devices Insulated gate field effect transistor Method of manufacturing junction field effect transistors Power metal-oxide-semiconductor-field-effect-transistor VMOS Mesa structure and manufacturing process VMOS Transistor and method of fabrication MOS Power transistor with improved high-voltage capability High performance submicron metal-oxide-semiconductor field effect transistor device structure Fabrication method for high power MOS device Method of fabricating mesa MOSFET using overhang mask Patent #: 4419811 InventorsAssigneeApplicationNo. 06/380170 filed on 05/20/1982US Classes:438/274, Short formed in recess in substrate257/341, Plural sections connected in parallel (e.g., power MOSFET)257/E21.42, With recess formed by etching in source/base contact region (EPO)257/E23.019, Consisting of layered constructions comprising conductive layers and insulating layers, e.g., planar contacts (EPO)257/E29.066, Body region structure of IGFET's with channel containing layer (DMOSFET or IGBT) (EPO)257/E29.259With nonplanar surface (EPO)ExaminersPrimary: Saba, William G.Attorney, Agent or FirmInternational ClassesH01L 21/336 (20060101)H01L 21/02 (20060101) H01L 29/02 (20060101) H01L 23/485 (20060101) H01L 29/10 (20060101) H01L 29/78 (20060101) H01L 29/66 (20060101) H01L 23/48 (20060101) AbstractA power MOSFET semiconductor structure is fabricated using the steps of depositing an epitaxial layer 12 of N conductivity type silicon on an underlying silicon substrate 10 of N conductivity type, forming a plurality of polycrystalline silicon electrodes 18 on the epitaxial layer 12, each electrode 18 being separated from the epitaxial layer 12 by a layer of insulating material 15; introducing P 30 and N 33 conductivity type impurities into the epitaxial layer 12 between the electrodes 18, the P type impurity 30 underlying the N type impurity 33; removing regions of the epitaxial layer 12 to form openings 21 in the epitaxial layer 12 between the electrodes 18, the removed regions 21 extending through the N type region 33 but not through the P type region 30; and depositing electrically conductive material 40 in the opening 23.The resulting semiconductor structure includes an N type substrate 10, an N type epitaxial layer 12, an opening 21 in the epitaxial layer 12 extending downward a selected distance, an upper N type region 33 surrounding the opening 21 and extending to the surface of the epitaxial layer 12, a lower P type region 30 which extends to the surface of the epitaxial layer 12 and everywhere separates the N type region 33 from epitaxial layer 12, an electrode 40 formed in the opening and extending to the upper surface of the epitaxial layer 12, and a second electrode 18 disposed above epitaxial layer 12 and separated from it by insulating material 15.Other References
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