Data interface mechanism for interfacing bit-parallel data buses of different bit width
Function integrated, shared ALU processor apparatus and method
Single chip MOS/LSI microcomputer with binary timer
Undirectional looped bus microcomputer architecture Patent #: 4378589
ApplicationNo. 06/619650 filed on 06/15/1984
US Classes:712/33, Having multiple internal buses712/36Application specific
ExaminersPrimary: Shaw, Gareth D.
Assistant: Malamud, Ronni S.
Attorney, Agent or Firm
International ClassesG06F 15/78 (20060101)
G06F 15/76 (20060101)
AbstractA system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16×16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.