Stacked interdigitated lead frame assembly
Patent 4496965 Issued on January 29, 1985. Estimated Expiration Date: 
January 9, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
January 9, 2004. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 1649741 3469017 3646409 3676748 Method for packaging hermetically sealed integrated circuit chips on lead frames Lead frame and chip carrier housing Patent #: 4195193 InventorsAssigneeApplicationNo. 06/568942 filed on 01/09/1984US Classes:257/666, LEAD FRAME257/669, With stress relief257/696, Bent (e.g., J-shaped) lead257/712, With provision for cooling the housing or its contents257/E23.042, Plurality of lead frames mounted in one device (EPO)257/E23.043Geometry of lead frame (EPO)ExaminersPrimary: James, Andrew J.Assistant: Lamont, John Attorney, Agent or FirmInternational ClassesH01L 23/495 (20060101)H01L 23/48 (20060101) AbstractAn integrated circuit package having a large number of external connections is assembled using two lead frames stacked one atop the other. The lead frames have complementary lead patterns which interdigitate to provide a very close lead spacing at the periphery of a semiconductor chip on which a complex integrated circuit is fabricated. | |
