Method for packaging hermetically sealed integrated circuit chips on lead frames
Lead frame and chip carrier housing Patent #: 4195193
ApplicationNo. 06/568942 filed on 01/09/1984
US Classes:257/666, LEAD FRAME257/669, With stress relief257/696, Bent (e.g., J-shaped) lead257/712, With provision for cooling the housing or its contents257/E23.042, Plurality of lead frames mounted in one device (EPO)257/E23.043Geometry of lead frame (EPO)
ExaminersPrimary: James, Andrew J.
Assistant: Lamont, John
Attorney, Agent or Firm
International ClassesH01L 23/495 (20060101)
H01L 23/48 (20060101)
AbstractAn integrated circuit package having a large number of external connections is assembled using two lead frames stacked one atop the other. The lead frames have complementary lead patterns which interdigitate to provide a very close lead spacing at the periphery of a semiconductor chip on which a complex integrated circuit is fabricated.