U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Systolic array apparatuses for matrix computations

Patent 4493048 Issued on January 8, 1985. Estimated Expiration Date: Icon_subject May 16, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

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Inventors

Assignee

Application

No. 06/494659 filed on 05/16/1983

US Classes:

708/607, Multiplication of matrices708/420Convolution

Examiners

Primary: Malzahn, David H.

Attorney, Agent or Firm

International Classes

G06F 17/15 (20060101)
G06F 15/76 (20060101)
G06F 15/80 (20060101)

Abstract

A systolic array system of inner product step processors is provided in the form of a mesh connected network which rhythmically compute and pass data through the system. Each processor in the system regularly feeds data in and out, each time performing some computation, so that a regular flow of data is kept up in the network. Many basic matrix computations can be readily and efficiently pipelined on systolic array network systems according to these inventions. Such arrays enjoy simple and regular communication paths and the individual processors in the networks are substantially all identical. Similar hexagonally connected processors can, for example, optionally perform matrix multiplication and LU-decomposition of a matrix. Linearly connected systolic arrays are useful for performing a variety of other computations.

Other References

  • Laws, Jr. et al., "A Cellular Array Multiplier for GF(2m)", IEEE Trans. on Computer, Dec. 1971, pp. 1573-1578
  • Chandra, "Matrix Multiplication on a Parallel Processing Machine", IBM Tech. Disclosure Bulletin, vol. 19, No. 12, May 1977, pp. 4830-4833
  • Swartzlander, Jr. et al., "Inner Product Computers", IEEE Trans. on Computers, vol. C-27, No. 1, Jan. 1978, pp. 21-31
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