Electronic microprocessor system having two cycle branch logic
Call and stack mechanism for procedures executing in different rings
Data processing system having centralized nonexistent memory address detection
Interruptible microprogram sequencing unit and microprogrammed apparatus utilizing same
Interruptable microprogram controller for microcomputer systems Patent #: 4438492
ApplicationNo. 06/446748 filed on 12/03/1982
US Classes:712/244, Exeception processing (e.g., interrupts and traps)710/262, Interrupt inhibiting or masking710/264, Interrupt prioritizing710/269Handling vector
ExaminersPrimary: Zache, Raulfe B.
Attorney, Agent or Firm
International ClassG06F 9/26 (20060101)
AbstractA computer system which facilitates the execution of nested subroutines and interrupts is disclosed. As each branch transfer within the program is executed by a control area logic, a microcommand initiates the transfer of the return address, which has been derived from the address in the present routine, to a first register of a push down stack. In addition, the microcommand also pushes down one level the contents of all of the registers in the stack containing previously stored return addresses. Thus, a sequential return to unfinished routines or subroutines is provided. When the subroutine or hardware interrupt service routine is completed, a code in the address field enables the return address of the previously branched from or interrupted routine to be retrieved from the first register in the push down stack and to provide it as the address of the next instruction to be executed. The retrieval of the return address from the push down stack also pops all other stored return addresses one level in the stack. In addition to providing multiple levels of subroutine and interrupt nesting, any number of subroutines or hardware interrupts may be partially completed since the last operating subroutine or hardware interrupt service routine is always the first one to be completed. Logic is also provided to detect the occurrence of a hardware interrupt during a return sequence such that the requirement to simultaneously push and pop the stack is properly handled.