Emitter coupled flip flop memory with complementary bipolar loads
Patent 4480319 Issued on October 30, 1984. Estimated Expiration Date: 
October 30, 2001. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 30, 2001. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3603820 3693057 Integrated logic elements with improved speed-power characteristics Integrated semiconductor circuit arrangement Patent #: 4323913 InventorsAssigneeApplicationNo. 06/228475 filed on 01/26/1981US Classes:365/155, Plural emitter or collector257/511, With complementary (npn and pnp) bipolar transistor structures257/539, Combined with bipolar transistor257/563, With multiple separately connected emitter, collector, or base regions in same transistor structure257/577, Including additional component in same, non-isolated structure (e.g., transistor with diode, transistor with resistor, etc.)326/101, SIGNIFICANT INTEGRATED STRUCTURE, LAYOUT, OR LAYOUT INTERCONNECTIONS326/126, Emitter-coupled or emitter-follower logic365/156ComplementaryExaminersPrimary: Larkins, William D.Attorney, Agent or FirmInternational ClassG11C 11/411 (20060101)Foreign Application Priority Data1978-01-25 JPAbstractDisclosed is a memory cell circuit including a pair of memory transistors having respective collectors and bases cross-coupled to each other, wherein load means connected to the collector of each one of said memory transistors comprises a parallel circuit of a load resistance and a transistor whose emitter and collector are connected to both ends of the load resistance and whose base is connected to the collector of the other of the memory transistors, thereby causing the readout currents of the memory cell circuit to be greater irrespective of increased load resistances.Other References
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