Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
January 3, 2003. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3750268 Double polycrystalline silicon gate memory device Method of manufacturing electronic devices Self aligned method for making bipolar transistor having minimum base to emitter contact spacing Method for forming a narrow dimensioned region on a body Self-aligned metal process for integrated injection logic integrated circuits Self-aligned metal process for field effect transistor integrated circuits Self-aligned metal process for integrated circuit metallization Patent #: 4400865 InventorApplicationNo. 06/455386 filed on 01/03/1983US Classes:438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)257/E21.158, Manufacture of electrode on semiconductor body using process other than by epitaxial growth, diffusion of impurities, alloying of impurity materials, or radiation bombardment (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.507, Formation of contacts to semiconductor by use of metal layers separated by insulating layers, e.g., self-aligned contacts to source/drain or emitter/base (EPO)438/301, Source or drain doping438/303, Utilizing gate sidewall structure438/586, Combined with formation of ohmic contact to semiconductor region438/947Subphotolithographic processingExaminersPrimary: Saba, William G.Attorney, Agent or FirmInternational ClassesH01L 21/336 (20060101)H01L 21/60 (20060101) H01L 21/02 (20060101) H01L 21/28 (20060101) AbstractA self-aligned metal process and resulting structure is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. All gate electrodes are composed of polysilicon while the remaining contacts are composed of metal. The insulation between the metal contacts and the polysilicon is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A first layer of polysilicon is formed thereover. Openings are made in the polysilicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal and vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is formed hereat. A second polysilicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions. The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions.Other References
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