Trim network for monolithic circuits and use in trimming a d/a converter
Digital-to-analog converter with improved compensation arrangement for offset voltage variations
Monolithic integrable R-2R network Patent #: 4381499
ApplicationNo. 06/374886 filed on 05/04/1982
US Classes:323/354, Selective333/81R, ATTENUATORS341/138, Nonlinear341/144, Digital to analog conversion455/249.1Variable attenuator type
ExaminersPrimary: Wong, Peter S.
Attorney, Agent or Firm
International ClassH03H 7/24 (20060101)
Foreign Application Priority Data1981-05-07 JP
AbstractA ladder-type signal attenuator comprises a ladder network (50) storing a ladder resistor circuit of a plurality of stages (n-1) each having an input resistor (2R) and an output resistor (R) and a ladder portion of the final stage (n) having an input resistor (8) and an output resistor (7) and coupled to the ladder resistor circuit. The resistance value (RB) of the input resistor (8) of the ladder portion of the final stage is different from 2R and/or the resistance value (RA) of the output resistor (7) is different from R. A bias voltage (Vb) or an analog input signal (Sin) is selectively applied to a corresponding signal input terminal of the ladder circuit (50) by means of switches (S1 to Sn) in response to control data (b1 to bn) of n bits. At least one of the resistance values of the two resistors (7, 8) of the final stage ladder portion is changed as a function of the state "0" or "1" of the final bit (bn ) of the control data, whereby the ratio of the output to the input of the ladder-type signal attenuator with respect to the control data is approximated in a polygonal line manner to a desired curve.