Abstract

A communication adapter circuit (10) is connected to a processor through a data bus (12)and a control bus (14). Data and control signals are provided through the buses (12,14) to a timer circuit (18), a programmable peripheral interface circuit (20), an asynchronous and bisynchronous control circuit (22) and an SDLC/HDLC control circuit (24). Each of the control circuits (22, 24) includes parallel-to-serial and serial-to-parallel conversion circuitry. A clock select circuit (32) operates in conjunction with the timer circuit (18) and the programmable peripheral interface circuit (20) to establish a data transmission rate for the data flow through the adapter circuit (10). From the control circuits (22, 24) the data is transmitted through a bi-directional serial line (44) to a dual modem switch (56). From the switch (56) the data is transmitted to either an EIA interface circuit (60) to a conventional modem or through a line (64) to an internal modem.

Other References

• Proceedings of the National Electronics Conference, vol. 31, 1977, pp. 300-304, G. J. Summers, "Microprocessor Controlled LSI in Data Communication Links.
• Electronic Engineering, vol. 52, No. 642, Sep. 1980, pp. 111, 113, 117, 119 and 122, G. P. Sawyer et al., "New Concepts in Single Board Computers.
• E.D.N. vol. 23, No. 1, Jan. 1978, pp. 61-67, A. Hirsch, "Minis Used as Data Interfaces Merit Multi-Level Considerations.
• Intel-MCS-80/85™ Family Users' Manual, Oct. 1979
• Krutz, "Microprocessors and Logic Design", 1980, John Wiley & Sons, Section 8.1-8.5
• Electronics, Sep. 1977, Qugle, "Using Bar Meter Displays Lowers Panel Meter Costs.