Storage hierarchy performance monitor
Cache write capacity
Input-output unit having extended addressing capability
Hash index table hash generator apparatus
Hierarchical data storage system
Method and means for the sharing of data resources in a multiprocessing, multiprogramming environment
Methods and apparatus for resetting peripheral devices addressable as a plurality of logical devices
Computer having an indexed local ram to store previously translated virtual addresses Patent #: 4410941
ApplicationNo. 06/293648 filed on 08/17/1981
US Classes:711/205Directories and tables (e.g., DLAT, TLB)
ExaminersPrimary: Shaw, Gareth D.
Assistant: Dorsey, Dennis L.
Attorney, Agent or Firm
International ClassesG06F 12/08 (20060101)
G06F 17/30 (20060101)
AbstractA cache is accessed based upon addresses to a backing store having a larger address space than the cache. The backing store consists of plurality of devices exhibiting delay access boundaries. The cache accessing is based upon a hashing method and system derived from the arrangement of the backing store and in an ordered manner for accommodating the delay access boundaries and enable rapidly adjusting the hash parameters in accordance with changes and backing store capability in other hardware changes.