U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method of fabricating a monolithic integrated circuit structure

Patent 4463491 Issued on August 7, 1984. Estimated Expiration Date: Icon_subject April 23, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Method of making a semiconductor device
Patent #: 4069067
Issued on: 01/17/1978
Inventor: Ichinohe

4280272

Use of silicide to bridge unwanted polycrystalline silicon P-N junction Patent #: 4333099
Issued on: 06/01/1982
Inventor: Tanguay ,   et al.

Inventors

Assignee

Application

No. 06/371325 filed on 04/23/1982

US Classes:

438/233, And contact formation257/369, Complementary insulated gate field effect transistors257/382, With contact to source or drain region of refractory material (e.g., polysilicon, tungsten, or silicide)257/E21.166, Conductive layer comprising semiconducting material (EPO)257/E21.641, Interconnection or wiring or contact manufacturing related aspects (EPO)257/E21.642, Isolation region manufacturing related aspects, e.g., to avoid interaction of isolation region with adjacent structure (EPO)257/E27.067, Including both N- and P- wells in the substrate, e.g. twin-tub (EPO)438/215, Having fuse or integral short438/453, And electrical conductor formation (i.e., metallization)438/621, Contacting diversely doped semiconductive regions (e.g., p-type and n-type regions, etc.)438/647Having electrically conductive polysilicon component

Examiners

Primary: Weisstuch, Aaron
Assistant: Auyang, Hunter L.

Attorney, Agent or Firm

International Classes

H01L 21/285 (20060101)
H01L 21/70 (20060101)
H01L 21/02 (20060101)
H01L 21/8238 (20060101)
H01L 27/092 (20060101)
H01L 27/085 (20060101)

Abstract

Method of fabricating a monolithic integrated circuit structure incorporating complementary metal-oxide-silicon field effect transistors (CMOS FET's) including providing a body of silicon produced by conventional techniques having a sector of N-type and a sector of P-type each covered by a thin silicon oxide layer and a thin silicon nitride layer. The regions of the body adjacent to each of the sectors are covered by a thicker silicon oxide field layer. Portions of the thin nitride and oxide layers are removed to expose spaced apart zones in each of the sectors. Adherent contact members of low resistivity polycrystalline silicon of N and P-type conductivity are formed in contact with the exposed surfaces of the zone in the P and N-type sectors, respectively. Where N and P-type contact members are contiguous a rectifying junction is produced. The surfaces of the polycrystalline contact members are metallized with a highly conductive material, thereby shorting out the rectifying junctions. P-type conductivity imparting material is implanted through a gate oxide layer into the N-type sector except the portion shielded by a first gate electrode and the contact members. N-type conductivity imparting material is implanted through a gate oxide layer into the P-type sector except the portions shielded by a second gate electrode and the contact members. The body is heated to drive the implanted conductivity type imparting materials further into the sectors and to diffuse conductivity type imparting material from the contact members into the adjacent zones.

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