Integrated digital semiconductor circuit Patent #: 4400802
ApplicationNo. 06/346199 filed on 02/05/1982
US Classes:365/226, POWERING365/227Conservation of power
ExaminersPrimary: Fears, Terrell W.
Attorney, Agent or Firm
International ClassesG11C 11/419 (20060101)
G11C 7/00 (20060101)
G11C 7/20 (20060101)
G11C 11/417 (20060101)
Foreign Application Priority Data1981-02-06 JP
AbstractA static type semiconductor memory device has a power down mode in which an operating voltage for peripheral circuits, such as decoder circuits, is turned off when the memory chip is in a non-selected condition. The static type semiconductor memory device comprises first transistors, which are connected to a pair of data buses and which pull down the potentials of the pair of data buses to a medium potential when the memory chip has changed from a selected condition, to the non-selected condition and second transistors which are connected to the pair of data buses and which pull up the potentials of the pair of data buses to a high potential when the memory chip has changed from a non-selected condition to a selected condition.