Tester for LSI devices and memory devices
Patent 4450560 Issued on May 22, 1984. Estimated Expiration Date: 
October 9, 2001. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 9, 2001. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesInventorAssigneeApplicationNo. 06/309981 filed on 10/09/1981US Classes:714/736, Device response compared to expected fault-free response714/718, Memory testing714/724, Digital logic testing714/744Clock or synchronizationExaminersPrimary: Atkinson, Charles E.International ClassesG01R 31/319 (20060101)G01R 31/28 (20060101) G11C 29/56 (20060101) AbstractA single tester tests both LSI and memory devices by storing test signals and standards for the pins of LSI devices in a storage element, providing test signals and standards for the data pins of memory devices from a generator, and selectably routing the test signals and standards from the storage element for LSI testing and from the generator for memory testing; format and timing information for each test signal and standard (for LSI testing) or for groups of test signals and standards (for memory testing) is stored in a second storage element and addresses corresponding to each test signal and standard (for LSI testing) or to each group of test signals and standards (for memory testing) and selectably provided to the second storage element. | |
