Method of fabricating a semiconductor device with a base region having a deep portion
Patent 4443931 Issued on April 24, 1984. Estimated Expiration Date: 
June 28, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 28, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of manufacturing a gate turn-off thyristor Method of manufacturing junction field effect transistors Integrated circuit method Method for manufacturing semiconductor integrated circuits utilizing special contact formation MOS Power transistor with improved high-voltage capability Patent #: 4345265 InventorsApplicationNo. 06/392870 filed on 06/28/1982US Classes:438/138, Vertical channel257/124, Combined with field effect transistor structure257/335, Active channel region has a graded dopant concentration decreasing with distance from source region (e.g., double diffused device, DMOS transistor)257/914, POLYSILICON CONTAINING OXYGEN, NITROGEN, OR CARBON (E.G., SIPOS)257/E21.033, Comprising inorganic layer (EPO)257/E29.066, Body region structure of IGFET's with channel containing layer (DMOSFET or IGBT) (EPO)257/E29.198, Transistor with vertical current flow (EPO)257/E29.257, Having vertical bulk current component or current vertically following trench gate (e.g., vertical power DMOS transistor) (EPO)438/273, Having integral short of source and base regions438/545, Forming partially overlapping regions438/546Plural dopants in same region (e.g., through same mask opening, etc.)ExaminersPrimary: Ozaki, G.Attorney, Agent or FirmInternational ClassesH01L 29/02 (20060101)H01L 21/033 (20060101) H01L 29/739 (20060101) H01L 29/66 (20060101) H01L 21/02 (20060101) H01L 29/78 (20060101) H01L 29/10 (20060101) AbstractA semiconductor device, such as a MOSFET or IGR, is fabricated with a base region having a deep portion for reducing parasitic currents. A wafer is provided having an N type layer on an appropriately doped substrate. A first oxide layer is formed on the wafer, and a refractory electrode layer is deposited on the first oxide layer. A first window is opened in the refractory electrode layer, and then silicon nitride is deposited on the wafer. A second window is opened in the silicon nitride layer, within the first window. A deep P+ base region is diffused into the wafer through the second window, and then a second oxide layer is selectively grown in the second window. The silicon nitride layer is selectively removed, thereby opening a third window, defined by the second window and the second oxide layer situated within the second window. A shallow P base region is diffused into the wafer through the third window, followed by diffusion of a shallow N+ region through the third window. The P-N junction between the N+ region and the deep P+ base region terminates at the surface of the wafer. The second oxide layer is removed, exposing the P-N junction, and the wafer is metallized, thereby implementing an electrical short across the P-N junction.Other References
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