U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Preprocessing circuitry apparatus for digital data

Patent 4442542 Issued on April 10, 1984. Estimated Expiration Date: Icon_subject January 29, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3432673

3898617

Method of inspecting circuit boards and apparatus therefor
Patent #: 4152723
Issued on: 05/01/1979
Inventor: McMahon ,   et al.

Device for examination of distances in a picture
Patent #: 4223387
Issued on: 09/16/1980
Inventor: Danielsson ,   et al.

Apparatus for processing digital data representative of a two-dimensional image Patent #: 4300122
Issued on: 11/10/1981
Inventor: McMahon

Inventors

Assignee

Application

No. 06/344245 filed on 01/29/1982

US Classes:

382/147, Inspecting printed circuit boards382/203Shape and form analysis

Examiners

Primary: Boudreau, Leo H.
Assistant: McDowell, Erin A.

Attorney, Agent or Firm

International Class

G06T 7/00 (20060101)

Abstract

An apparatus for analyzing line sequential binary data generated by scanning a printed circuit board with a scanning laser apparatus is disclosed. The circuit board contains conducting strips on an electrically insulated substrate. The conductors can be characterized by the number and the locations of their corners and by their widths and by the widths of the substrate occurring between parallel and spaced apart conductors. The line sequential data when viewed together forms a two dimensional image array of the circuit board and the two dimensional array contains information about the conducting corners, widths, etc. The line sequential binary data is first smoothed by smoothing circuits to eliminate errors due to noise, scanning equipment tolerances, etc. Then the smoothed data in line sequential format is transmitted to a corner recognition and pairing circuit where the corner features of the conductors are recognized. Because of digitizing errors, a corner feature often appears as two, three or more vertically and/or horizontally adjacent corner pairs. The excess corners are eliminated by the corner recognition and pairing circuit. At the same time, a line/space width error detection circuit portion of the apparatus examines the widths of the horizontal and vertically directed conducting strips and the spaces between them. If any of the conductors or spaces fall below a predetermined minimum over a predetermined length of the conductor or strip an error signal is generated.

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