Method for making a base etched transistor integrated circuit
Patent 4435898 Issued on March 13, 1984. Estimated Expiration Date: 
March 22, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 22, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3312881 3489622 3551220 3669760 3677837 3717515 3926695 Dielectrically isolated semiconductor devices Method of fabricating high-gain transistors Silicon etching process InventorsApplicationNo. 06/360731 filed on 03/22/1982US Classes:438/369, Dopant implantation or diffusion257/592, With base region having specified doping concentration profile or specified configuration (e.g., inactive base more heavily doped than active base or base region has constant doping concentration portion (e.g., epitaxial base))257/E21.218, Plasma etching; reactive-ion etching (EPO)257/E29.044, Base region of bipolar transistors (EPO)257/E29.185, Having emitter-base junction and base-collector junction on different surfaces (e.g., mesa planar transistor) (EPO)438/16, Optical characteristic sensed438/362, Recessed oxide by localized oxidation (i.e., LOCOS)438/712, Reactive ion beam etching (i.e., RIBE)438/9Plasma etchingExaminersPrimary: Saba, W. G.Attorney, Agent or FirmInternational ClassesH01L 29/02 (20060101)H01L 29/732 (20060101) H01L 21/02 (20060101) H01L 29/66 (20060101) H01L 21/3065 (20060101) H01L 29/10 (20060101) AbstractA process is described which permits the fabrication of very narrow base width bipolar transistors. The ability to selectively vary the transistor characteristics provides a degree of freedom for design of integrated circuits. The bipolar transistor is processed up to the point of emitter formation using conventional techniques. But, prior to the emitter formation, the base area which is to be the emitter is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitter and rest of the metallization. Since the intrinsic base under the emitter is etched. and the normal emitter is formed afterwards, the etching reduces the base width by an amount approximately equal to the etched depth. The transistor characteristics depend strongly upon the base width so the etching is controlled to very tight dimensions.Other References
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