Memory system handling a plurality of bits as a unit to be processed
April 3, 2001. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3163850 3337860 3543240 3638199 3766520 3889234 3899771 Method and apparatus for accessing horizontal sequences and rectangular sub-arrays from an array stored in a modified word organized random access memory system Method and apparatus for accessing horizontal sequences, vertical sequences, and rectangular subarrays from an array stored in a modified word organized random access memory system Method and apparatus for accessing horizontal sequences, vertical sequences and regularly spaced rectangular subarrays from an array stored in a modified word organized random access memory system InventorsAssigneeApplicationNo. 06/250784 filed on 04/03/1981US Classes:382/282, Selecting a portion of an image345/544, Memory partitioning345/567, Using decoding382/305, Image storage or retrieval711/100STORAGE ACCESSING AND CONTROLExaminersPrimary: Smith, JerryAssistant: Niessen, William G. Attorney, Agent or FirmInternational ClassG06F 12/02 (20060101)AbstractA memory system for simultaneously extracting a desired block of data in response to an address specifying only the center bit of the block. The input address is modified through an arithmetic circuit wherein the address representing the center bit is added to and subtracted from to produce a plurality of addresses which are used to address a plurality of separate memory blocks. The outputs from the memory blocks are passed through a selection alignment matrix circuit which selects from the outputs of the memory blocks only those bits in the desired block of data and aligns those bits in a predetermined array. Bits other than those in the desired block of data are discarded. | |
