Abstract

An improved means and method for accomplishing floating point calculations in computational apparatus includes a primary microprocessor and a secondary microprocessor, each with its own control ROM. The normal or fixed point calculations are handled by the primary microprocessor under the control of a first segment of the associated control ROM. When a floating point calculation is called for, a second segment of that ROM is addressed. The addressing of the second segment of the first ROM also effects the coincident addressing of the ROM of the secondary microprocessor. For floating point calculations, the exponent portion of the numbers being manipulated is handled by the primary microprocessor. Simultaneously therewith, the mantissa portion of the numbers being manipulated is handled by the secondary microprocessor under the control of its associated control ROM. The resultant calculations are recombined in the primary microprocessor to produce a complete solution for the floating point calculation. In executing a division operation, the mantissas are preconditioned to be normalized, the most significant bit being a logical "1". The divide routine shifts and subtracts repeatedly until the most significant bit in an accumulating register is also a logical "1", thus eliminating the need for a preset counter and the associated control functions.

Other References

• Jeremiah et al., "Floating Point Multiply/Divide Assist", IBM Tech. Disclosure Bulletin, vol. 20, No. 5, Oct. 1977, pp. 1726-1727