U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Serial data bus communication system

Patent 4409656 Issued on October 11, 1983. Estimated Expiration Date: Icon_subject December 21, 2001. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3771134

Interrupt system for microprocessor system
Patent #: 4086627
Issued on: 04/25/1978
Inventor: Bennett, et al.

Interrupt status indication logic for polled interrupt digital system
Patent #: 4106091
Issued on: 08/08/1978
Inventor: Hepworth ,   et al.

Apparatus for giving priority to certain data signals
Patent #: 4208714
Issued on: 06/17/1980
Inventor: Eklund ,   et al.

Bus arbiter
Patent #: 4237534
Issued on: 12/02/1980
Inventor: Felix

Electronic data processing system for real time data processing
Patent #: 4257100
Issued on: 03/17/1981
Inventor: Syrbe ,   et al.

Data processing system incorporating arbiters and selectors to allocate transmissions by multiple devices on a bus Patent #: 4262357
Issued on: 04/14/1981
Inventor: Shima

Inventors

Assignee

Application

No. 06/333068 filed on 12/21/1981

US Classes:

709/250NETWORK-TO-COMPUTER INTERFACING

Examiners

Primary: Springborn, Harvey E.

Attorney, Agent or Firm

International Classes

G06F 13/36 (20060101)
G06F 13/366 (20060101)

Abstract

A node device for use in a digital data processing and communications system of the type utilizing a bus organization for facilitating the interconnection of a large plurality of digital data processing devices (user devices) in which redundant cables are employed. The node devices are interposed between the user devices and the redundant cables to permit automatic reconfiguration of the interconnection of the user devices in the event of malfunctioning or severing of one or more of the cable sets within a minimum period of time. The node devices provide the user devices with the structure needed to detect and diagnose system problems and to effect recovery procedures. In accordance with the invention, one of the plurality of nodes functions as the Bus Controller and by sampling the remaining nodes in the system, it determines the priority with which user devices may transmit or receive data over the bus. Each of the nodes employed is substantially identical and any one may be selected to function as the Bus Controller. Each includes a Microprogrammed Controller and necessary firmware to permit the controller to function in conjunction with special purpose hardware including a Programmable Logic Array (PLA) configured to perform a pre-processing function on control line inputs so that poll/response traffic on the active cables can continue with a minimum of delay.

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