Method of making silicon-on-sapphire FET
March 22, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSchottky gate field effect transistor Fabrication of a semiconductor component element having a Schottky contact and little series resistance utilizing special masking in combination with ion implantation Shadow masking process for forming source and drain regions for field-effect transistors and like regions Insulated gate field effect silicon-on-sapphire transistor and method of making same Method of fabricating improved short channel MOS devices utilizing selective etching and counterdoping of polycrystalline silicon Method of fabrication of self-aligned metal-semiconductor field effect transistors Low leakage N-channel SOS transistors and method of making them Self-aligned narrow gate MESFET process Integrated circuit manufacturing method Patent #: 4277883 InventorsApplicationNo. 06/360548 filed on 03/22/1982US Classes:438/149, On insulating substrate or layer (e.g., TFT, etc.)257/260, Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell)257/E29.05, Of field-effect transistors (EPO)257/E29.312, With PN junction gate (e.g., PN homojunction gate) (EPO)257/E29.314, Thin-film JFET (EPO)257/E29.32, Thin-film MESFET (EPO)438/174, Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)438/194Doping of semiconductive channel region beneath gate (e.g., threshold voltage adjustment, etc.)ExaminersPrimary: Roy, UpendraAttorney, Agent or FirmInternational ClassesH01L 29/812 (20060101)H01L 29/02 (20060101) H01L 29/66 (20060101) H01L 29/10 (20060101) H01L 29/808 (20060101) AbstractJunction and metal-semiconductor field effect transistors have a sapphire substrate to realize isolation and reduced capacitance, and have a self-aligned gate to minimize source parasitic resistance. A lightly doped, opposite conductivity type region under the channel forces carriers to flow near the silicon surface where mobility is high; this region is depleted at all times by the P-N junction built-in voltage and acts as an insulator. These devices serve as switches in high speed logic applications and as microwave amplifiers.Other References
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