MOS Integrated circuit having refractory metal or metal silicide interconnect layer
Patent 4392150 Issued on July 5, 1983. Estimated Expiration Date: 
October 27, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 27, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3381182 3537174 Structure for shallow junction MOS circuits Patent #: 4291322 InventorApplicationNo. 06/200648 filed on 10/27/1980US Classes:257/304, Storage node isolated by dielectric from semiconductor substrate257/383, Contact of refractory or platinum group metal (e.g., molybdenum, tungsten, or titanium)257/757, Silicide of refractory or platinum group metal257/E23.164, Containing semiconductor material, e.g., polysilicon (EPO)257/E29.161, Silicide (EPO)438/586, Combined with formation of ohmic contact to semiconductor region438/647, Having electrically conductive polysilicon component438/655SilicideExaminersPrimary: James, Andrew J.Attorney, Agent or FirmInternational ClassesH01L 29/40 (20060101)H01L 23/52 (20060101) H01L 23/532 (20060101) H01L 29/49 (20060101) AbstractA partial silicide layer under a polycrystalline silicon (polysi) first level interconnect reduces the sheet resistance of the first level interconnect. The polysi insulates the silicide from possibly reactive materials and gases. Since the silicide is not deposited over contacts between the polysi and the substrate, conventional polysi/silicon ohmic contacts can be made.Other References
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