ApplicationNo. 06/108911 filed on 12/31/1979
US Classes:716/17Programmable integrated circuit (e.g., basic cell, standard cell, macrocell)
ExaminersPrimary: Shaw, Gareth D.
Assistant: Heckler, Thomas M.
Attorney, Agent or Firm
International ClassG06F 17/50 (20060101)
AbstractA system and method for analysis of circuits which include a large number of circuit elements. Blocks of circuitry which define logical circuit functions such as gates and latches are set up as macromodels. Each macromodel need be represented in its full detail only once. Means are provided to recognize latency, or quiescence, of macromodels so that time may be saved in the circuit analysis when a macromodel is latent.