Method of making double level polysilicon series transistor devices
January 26, 2002. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod of making N-channel MOS integrated circuits Integrated circuit device Triple layer polysilicon cell Double level polysilicon series transistor cell Random access memory cell with different capacitor and transistor oxide thickness Substrate coupled floating gate memory cell High voltage MOSFET with inter-device isolation structure Double level polysilicon series transistor devices Patent #: 4319263 InventorAssigneeApplicationNo. 06/342953 filed on 01/26/1982US Classes:438/279, Making plural insulated gate field effect transistors having common active region257/366, Overlapping gate electrodes257/E21.209, Making electrode structure comprising conductor-insulator-conuctor-insulator-semiconductor, e.g., gate stack for non-volatile memory (EPO)257/E27.06, Field-effect transistor with insulated gate (EPO)257/E29.264, With multiple gate structure (EPO)438/266, Having additional, nonmemory control electrode or channel portion (e.g., for accessing field effect transistor structure, etc.)438/283Plural gate electrodes (e.g., dual gate, etc.)ExaminersPrimary: Ozaki, G.Attorney, Agent or FirmInternational ClassesH01L 21/02 (20060101)H01L 29/66 (20060101) H01L 29/78 (20060101) H01L 21/28 (20060101) H01L 27/085 (20060101) H01L 27/088 (20060101) AbstractA plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask. | |
