Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
July 8, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3750268 Double polycrystalline silicon gate memory device Method of manufacturing electronic devices Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching Method for forming an insulator between layers of conductive material High performance bipolar device and method for making same Self aligned method for making bipolar transistor having minimum base to emitter contact spacing Method for forming a narrow dimensioned region on a body Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation Self-aligned process for providing an improved high performance bipolar transistor InventorApplicationNo. 06/167172 filed on 07/08/1980US Classes:438/291, Using channel conductivity dopant of opposite type as that of source and drain257/346, Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate)257/E21.038, Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)257/E21.3, Post treatment (EPO)257/E21.431, With source and drain recessed by etching or recessed and refi lled (EPO)257/E21.432, With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO)257/E21.583Planarization; smoothing (EPO)ExaminersPrimary: Rutledge, L. DewayneAssistant: Saba, William G. Attorney, Agent or FirmInternational ClassesH01L 21/336 (20060101)H01L 21/033 (20060101) H01L 21/02 (20060101) H01L 21/768 (20060101) H01L 21/70 (20060101) H01L 21/321 (20060101) AbstractA process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The method for forming integrated circuits with this structure includes forming openings in a first polycrystalline silicon layer overlying an insulator by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is formed hereat. A second polycrystalline silicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions. The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions. A blanket layer of a plastic material is used to planarize the surface by reactive ion etching the plastic material and the conductive layer until the tops of the narrow dimensioned regions are reached. The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less. The source and drain electrodes are thusly formed.Other References
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