High speed NXM bit digital, repeated addition type multiplying circuit

Patent 4369500 Issued on January 18, 1983. Estimated Expiration Date:

October 20, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

3670956

3691359

3743824

3752971

3767906

3900724

Binary parallel adder employing high speed gating circuitry
Patent #: 3932734
Issued on: 01/13/1976
Inventor: Parsons

Propagation line adder and method for binary addition
Patent #: 4031379
Issued on: 06/21/1977
Inventor: Schwartz

Binary adder
Patent #: 4052604
Issued on: 10/04/1977
Inventor: Maitland , et al.

Single line propagation adder and method for binary addition Patent #: 4152775
Issued on: 05/01/1979
Inventor: Schwartz

Inventor

Fette, Bruce

Application

No. 06/198688 filed on 10/20/1980

US Classes:

708/626, Sum of cross products708/709Adding more than two numbers

Examiners

Primary: Malzahn, David H.

Attorney, Agent or Firm

Parsons; Eugene A.

International Classes

G06F 7/52 (20060101)
G06F 7/48 (20060101)
G06F 7/50 (20060101)

Abstract

N (M+1) combining circuits mathematically arranged into M addition rows and a final carry resolution row so as to form N+M-1 columns, each column having an output, an N-bit multiplicand and an M-bit multiplier being connected to the combining circuits to provide digital, repeated addition type multiplication of the numbers represented by the N and M bits. The combining circuits in the final carry resolution row each have a carry bit input connected to the carry bit output of the previous combining circuit and an inverting amplifier is included in the carry propagation line every three or four combining circuits, to regenerate the carry bit. Further the entire multiplying circuit is formed on a single semiconductor chip and includes N inputs pads and N output pads with input latches and output latches for operating on both the N input bits and the M input bits with very little loss in time.