U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Computer system with power control circuit

Patent 4365290 Issued on December 21, 1982. Estimated Expiration Date: Icon_subject December 21, 1999. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3643219

3703710

3805796

3833005

3922526

Reducing power consumption in calculators
Patent #: 3941989
Issued on: 03/02/1976
Inventor: McLaughlin ,   et al.

Portable data entry apparatus
Patent #: 3956740
Issued on: 05/11/1976
Inventor: Jones ,   et al.

Precessing display pager
Patent #: 3976995
Issued on: 08/24/1976
Inventor: Sebestyen

Switching control circuits for electronic calculator with push-button on-off system
Patent #: 4089062
Issued on: 05/09/1978
Inventor: McElroy, et al.

System for operating volatile memory in normal and standby modes
Patent #: 4130899
Issued on: 12/19/1978
Inventor: Bowman ,   et al.

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Inventors

Assignee

Application

No. 06/019625 filed on 03/12/1979

US Classes:

713/321, Programmable calculator with power saving feature365/227, Conservation of power607/16Intermittent operation for energy conservation

Examiners

Primary: Shaw, Gareth D.
Assistant: Chan, Eddie P.

Attorney, Agent or Firm

International Classes

A61N 1/372 (20060101)
A61N 1/365 (20060101)

Abstract

A digital computer system is described as comprising an input data circuit, a processor for executing a program stored in a memory to process the inputted data, a depletable energy source (e.g., a battery) for energizing the elements of the computer system, and a power control circuit for selectively controlling the drain imposed upon the energy source in accordance with the data input into the system and the program executed by the processor. In an illustrative embodiment of this invention, the power control circuit is operative in at least three modes of operation, namely off/rest, power down, and operating. In the off/rest mode, the power control circuit imposes a minimum power drain upon the depletable energy source. An operator may manipulate a switch or actuation means to apply a transition signal to the power control, whereby the computer system is disposed from its off/rest mode to its power down mode. In the power down mode, the control circuit applies power at an intermediate level to the data input means. In an illustrative embodiment of this invention, the data input means includes a keyboard and a decoder for providing a signal indicative that one of the keys has been depressed. Upon actuation of the key, a data available signal DA is transmitted to the power control circuit, whereby the computer system is disposed in its operating mode, wherein all of the elements of the computer system are energized at a high power level. In its operating mode, the processor and its memory are fully energized to execute the stored program.

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