Self-aligned metal process for field effect transistor integrated circuits
Patent 4359816 Issued on November 23, 1982. Estimated Expiration Date: 
July 8, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 8, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3643235 3648125 3750268 3823353 3922565 Semiconductor devices and methods of manufacturing same Double polycrystalline silicon gate memory device Method for fabricating FET one-device memory cells with two layers of polycrystalline silicon and fabrication of integrated circuits containing arrays of the memory cells charge storage capacitors utilizing five basic pattern deliberating steps Method of manufacturing electronic devices Insulated-gate field-effect transistor with self-aligned contact hole to source or drain InventorsApplicationNo. 06/167253 filed on 07/08/1980US Classes:438/251, Including doping of semiconductive region257/E21.036, Characterized by their size, orientation, disposition, behavior, shape, in horizontal or vertical plane (EPO)257/E21.038, Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)257/E21.3, Post treatment (EPO)257/E21.429, Using etching to form recess at gate location (EPO)257/E21.432, With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO)257/E21.433, Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO)257/E21.434, With initial gate mask or masking layer complementary to prospective gate location, e.g., with dummy source and drain contacts (EPO)257/E21.443, Using self-aligned punch through stopper or threshold implant under gate region (EPO)257/E21.444, Using dummy gate wherein at least part of final gate is self-aligned to dummy gate (EPO)257/E21.646, Dynamic random access memory structures (DRAM) (EPO)257/E29.112, Characterized by their shape, relative sizes or dispositions (EPO)438/289, Doping of semiconductive channel region beneath gate insulator (e.g., adjusting threshold voltage, etc.)438/297, Recessed oxide formed by localized oxidation (i.e., LOCOS)438/303Utilizing gate sidewall structureExaminersPrimary: Ozaki, G.Attorney, Agent or FirmInternational ClassesH01L 21/336 (20060101)H01L 21/033 (20060101) H01L 21/70 (20060101) H01L 29/40 (20060101) H01L 29/41 (20060101) H01L 21/02 (20060101) H01L 21/321 (20060101) H01L 21/8242 (20060101) AbstractA process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistors. The insulation between the contacts and the metal is dielectric material having a thickness dimension about a micron or less. The structure is substantially planar. The method for forming this structure involves providing a silicon body and then forming a first insulating layer on the silicon body. A layer of polycrystalline silicon is formed thereover. Openings are made in the layer by reactive ion etching which results in the structure having horizontal surfaces and vertical surfaces. The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer is then formed on both the horizontal surfaces and vertical surfaces. Reactive ion etching of this second insulating layer moves the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation. The remaining polycrystalline layer is removed to leave the narrow regions on the major surface of the silicon body. A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions and form the gate electrodes.Other References
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