Abstract

A floating gate memory cell has its control gate self-aligned to the floating gate in the source to drain direction and its floating gate self-aligned to the channel region in that direction and the direction transverse thereto without overlaying the field oxide. The cell may be manufactured by the following method: forming insulation such as silicon oxide over the substrate to serve as gate oxide; forming a conductor such as polysilicon over the insulation; etching the polysilicon to a patterned mask and using the mask to dissolve the unprotected oxide to leave a future floating gate of polysilicon overlaying and coextensive with the future channel region in the direction transverse to the source-to-drain region; overlaying insulation such as a further oxide and then overlaying a second conductor such as polysilicon, which is thus insulated from the floating gate; patterning this second polysilicon, which will serve as a control gate, with a photo resist mask to etch the second conductor to form a control gate, and to preferentially remove enough oxide to expose the unmasked portion of the future floating gate, and etching this unmasked portion. Thus, the floating gate is self-aligned to the channel in the source-to-drain direction, as well as in the direction transverse to the source-to-drain direction. The remaining insulation may now be dissolved using the gates as masks to expose the source and drain regions.