Identification of a faulty address decoder in a function unit of a computer having a plurality of function units with redundant address decoders
System for monitoring the validity of electrical data fed to a number of n functionally parallel-connected data channels
Processing system with dual buses
Fault-tolerant interface circuit for parallel digital bus Patent #: 4298982
ApplicationNo. 06/227859 filed on 01/23/1981
US Classes:714/48, Error detection or notification714/819Comparison of data
ExaminersPrimary: Atkinson, Charles E.
Attorney, Agent or Firm
International ClassesG06F 11/10 (20060101)
G06F 5/01 (20060101)
AbstractApparatus for checking the correct operation of a parallel byte shifter of the type having a plurality of input ports connected to individual byte lines of a data bus. When predetermined byte lines to the byte shifters are selected, control means are provided to activate a set of shift select means connected to error checking circuits. The error checking circuits comprise logic gating means for checking the proper selection of byte lines and for storing a signal indicative of an error or absence of an input error in the error storage means. When the data byte is being transferred out or read out of the byte shifter, the error storage means is read out to determine the presence or absence of an output error from the error storage means.