Method for semiconductor memory testing
Patent 4335457 Issued on June 15, 1982. Estimated Expiration Date: 
August 8, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
August 8, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3252097 3478286 3619030 3820077 Method of and device for testing a digital memory Variable function digital word generating, receiving and monitoring device Portable circuit tester Patent #: 4108358 InventorAssigneeApplicationNo. 06/176353 filed on 08/08/1980US Classes:714/745, Determination of marginal operation limits714/720, Special test pattern (e.g., checkerboard, walking ones)714/723Error mapping or loggingExaminersPrimary: Atkinson, Charles E.Attorney, Agent or FirmInternational ClassG11C 29/56 (20060101)AbstractSemiconductor memory devices are tested by using a special purpose computer which uses simple test patterns to determine the weakest bits of the device and then tests only these relatively few "weak bits" and structurally and operationally adjacent bits using highly complex test patterns to determine if the device is functioning properly. This procedure considerably reduces testing time over that required using prior art techniques.Other References
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