Wave shaping circuit for electro-optical code readers
Patent 4335301 Issued on June 15, 1982. Estimated Expiration Date: 
September 27, 1999. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
September 27, 1999. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3751636 3752963 3784794 3892974 3909594 Hand held bar code reader with constant linear amplifier output Bar code scanner Method and apparatus to read in bar-coded information Patent #: 4140271 InventorsAssigneeApplicationNo. 06/079326 filed on 09/27/1979US Classes:235/462.25, Reader processing circuitry250/555, Including coded record327/165, Regenerating or restoring rectangular (e.g., clock, etc.) or pulse waveform327/184Rectangular (e.g., clock, etc.) or pulse waveform generating by conversion from input AC (e.g., sine, etc.) waveExaminersPrimary: Yusko, Donald J.Attorney, Agent or FirmInternational ClassG06K 7/10 (20060101)AbstractAn electrical output signal from an electro-optical code reader is amplified (U1) to develop a first signal which is applied to a positive peak detector (U2D1, C2) and a negative peak detector (U3, D2, C3). The positive peak detector provides a second signal whose voltage level follows that of the first signal as the first signal increases, from the time that the voltage level of the second signal is brought substantially equal to that of the first signal to the time that the first signal begins to decrease, with the voltage level of the second signal thereafter being maintained substantially constant. The negative peak detector provides a third signal whose voltage level follows that of the first signal as the first signal decreases from the time that the voltage level of the third signal is brought substantially equal to that of the first signal to the time that the first signal begins to increase, with the third signal thereafter being maintained substantially constant. The second and third signals are combined (R5,R6) top provide a reference signal whose voltage level is intermediate those of the second and third signals. A comparator (U4) provides a circuit output signal which has a first logic level when the voltage level of the first signal exceeds that of the reference signal and which has a second logic level when the voltage level of the reference signal exceeds that of the first signal. The logic level transitions in the circuit output signal are detected (C4, R10, D6, R11; U5, C5, R9, D7, R 8) to develop pulses which momentarily close fast-acting semiconductor switches (S1, S2) associated with the positive and negative peak detectors, whereby the voltage level of the second signal is brought to that of the first signal at the time that the voltage level of the first signal goes above that of the reference signal, and whereby the voltage level of the third signal is brought to that of the first signal at the time that the voltage level of the first signal goes below that of the reference signal. | |
