U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Cache apparatus for enabling overlap of instruction fetch operations

Patent 4313158 Issued on January 26, 1982. Estimated Expiration Date: Icon_subject January 26, 1999. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3588829

Inventors

Assignee

Application

No. 05/968049 filed on 12/11/1978

US Classes:

711/140Cache pipelining

Examiners

Primary: Shaw, Gareth D.
Assistant: Eng, David Y.

Attorney, Agent or Firm

International Classes

G06F 12/08 (20060101)
G06F 9/38 (20060101)

Abstract

A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes control apparatus, an instruction buffer for storing instructions received from main store and a transit block buffer comprising a plurality of locations for storing read commands. The control apparatus includes a plurality of groups of bit storage elements corresponding to the number of transit buffer locations. Each group includes at least a pair of instruction fetch indicator elements which are operatively connected to control the writing of first and second blocks of instructions into the instruction buffer. Each time a read command specifying the fetching of instructions of either a first or second block is received from the processing unit, the flag storage element associated with the transit block buffer location into which the read command is loaded is set to a binary ONE state while the corresponding ones of the flag storage elements associated with the other locations storing outstanding read commands specifying instruction fetches are reset to binary ZEROS. This permits only those instructions received from main store in response to that read command to be loaded into a specified section of the instruction buffer for enabling overlaps in processing several commands specifying instruction fetch operations.

PatentsPlus Images
Enhanced PDF formats
loading...
PatentsPlus: add to cart
PatentsPlus: add to cartSearch-enhanced full patent PDF image
$9.95more info
PatentsPlus: add to cart
PatentsPlus: add to cartIntelligent turbocharged patent PDFs with marked up images
$18.95more info
 
Sign InRegister
Username  
Password   
forgot password?