Process for production of integrated MOS circuits with and without MNOS memory transistors in silicon-gate technology
May 29, 2000. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3798752 Method for manufacturing a semiconductor field effort transistor MOSFET transistor and method of fabrication Method of fabricating field effect transistors having self-registering electrical connections between gate electrodes and metallic interconnection lines, and fabrication of integrated circuits containing the transistors Memory type insulating gate field effect semiconductor device Method of making a MOS device Process for fabricating insulated-gate field-effect transistors with self-aligned contacts Process for forming field dielectric regions in semiconductor structures without encroaching on device regions Method of stabilizing semiconductor device by converting doped poly-Si to polyoxides MNOS memory device InventorsApplicationNo. 06/154316 filed on 05/29/1980US Classes:438/200, And additional electrical device257/324, Multiple insulator layers (e.g., MNOS structure)257/394, With means to prevent parasitic conduction channels257/E21.033, Comprising inorganic layer (EPO)257/E21.337, Through-implantation (EPO)257/E21.625, With particular manufacturing method of gate insulating layer, e.g., different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants (EPO)438/217, Doping of semiconductor channel region beneath gate insulator (e.g., threshold voltage adjustment, etc.)438/275, Making plural insulated gate field effect transistors of differing electrical characteristics438/287Gate insulator structure constructed of diverse dielectrics (e.g., MNOS, etc.) or of nonsilicon compoundExaminersPrimary: Ozaki, G.Attorney, Agent or FirmInternational ClassesH01L 21/8234 (20060101)H01L 21/02 (20060101) H01L 21/70 (20060101) H01L 21/033 (20060101) H01L 21/265 (20060101) Foreign Application Priority Data1979-06-13 DEAbstractIntegrated MOS circuits with and without MNOS memory transistors in silicon-gate technology are produced with overlapped contacts using a silicon nitride mask. After production of structured SiO2 layers on a p- or n- doped semiconductor substrate to separate active transistor zones in accordance with the so-called LOCOS process, a silicon nitride layer is deposited onto the surface and is then structured so that the zones in which a gate oxide is to be produced, are uncovered and during gate oxidation, the surface of this structured silicon nitride layer is converted into an oxynitride layer. In contrast to previously known processes, the invention provides self-aligned overlapped contacts with oversized contact holes. The silicon-nitride layer functions as an etch-stop during etching of an intermediate oxide. This avoids under-etching of the polysilicon during contact hole etching. The overlapped contacts allow a substantial increase in the packing and integration density of the so-produced circuits.Other References
| |
