Method of fabrication for field effect transistors (FETs) having a common channel stopper and FET channel doping with the channel stopper doping self-aligned to the dielectric isolation between FETS
Monolithic semiconductor mask programmable ROM and a method for manufacturing the same
Floating gate storage device and method of fabrication
Semiconductor integrated circuit device composed of insulated gate field-effect transistor Patent #: 4235010
ApplicationNo. 06/058501 filed on 07/18/1979
US Classes:438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)257/316, With additional contacted control electrode257/E21.328, Radiation treatment (EPO)257/E29.053, With nonuniform doping structure in channel region surface (EPO)257/E29.304, Charging by tunneling of carriers (e.g., Fowler-Nordheim tunneling) (EPO)438/258, Including additional field effect transistor (e.g., sense or access transistor, etc.)438/262, Including elongated source or drain region disposed under thick oxide regions (e.g., buried or diffused bitline, etc.)438/593Separated by insulator (i.e., floating gate)
ExaminersPrimary: Ozaki, G.
Attorney, Agent or Firm
International ClassesH01L 21/02 (20060101)
H01L 21/26 (20060101)
H01L 29/66 (20060101)
H01L 29/02 (20060101)
H01L 29/10 (20060101)
H01L 29/788 (20060101)
Foreign Application Priority Data1978-07-31 JP
AbstractIn a nonvolatile semiconductor memory which comprises a source region and a drain region formed on one surface of a semiconductor substrate having one conductivity type, a first insulating film formed on a channel region which is located between the source region and the drain region, a floating gate formed on at least a portion of the first insulating film and which is electrically floated, a control gate formed on the floating gate via a second insulating film, and high impurity concentration regions formed in or near a portion of the channel region and having the same conductivity type as that of the substrate, the floating gate is formed prior to the high impurity concentration regions, and the high impurity concentration regions are formed just outside the channel region by self-alignment with said floating gate using said floating gate as part of a mask.