Test pattern generating apparatus
Patent 4293950 Issued on October 6, 1981. Estimated Expiration Date: 
April 2, 1999. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 2, 1999. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3751649 On line PROM handling system Digital stimulus generating and response measuring means Analog and digital circuit tester Patent #: 4168527 InventorsAssigneeApplicationNo. 06/026246 filed on 04/02/1979US Classes:714/743, Addressing714/744Clock or synchronizationExaminersPrimary: Atkinson, Charles E.Attorney, Agent or FirmInternational ClassesG01R 31/28 (20060101)G01R 31/319 (20060101) G11C 29/10 (20060101) G11C 29/04 (20060101) G11C 29/56 (20060101) G01R 31/3181 (20060101) Foreign Application Priority Data1978-04-03 JPAbstractA test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted. | |
