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Digital computer monitoring and restart circuit Patent #: 4072852
AbstractPerformance monitor apparatus is adapted to monitor various computer program events such as the length of time required to execute a particular program, the number of times a particular program or instruction sequence is executed during some predetermined period, etc. The apparatus includes a buffer for receiving an instruction data word from a data processor and for temporarily storing the data word, a register having a plurality of bistable elements each of which is adapted to produce either a first or second output signal in response to receipt of a first or second operation signal respectively and receipt of a select signal, a select logic circuit for applying a select signal to a particular bistable element identified by certain bits of the instruction data word stored in the buffer, and an operation logic circuit for supplying to the bistable elements either a first or second operation signal as determined by certain other bits of the instruction data word stored in the buffer. Each bistable element represents a different event or occurrence in a computer program being monitored and the signals produced by the bistable elements indicate the nature of the monitoring operation to be performed. The signals are supplied to timing and counting apparatus which then either measures the time over which the signals are produced or increments a count in response to receiving the signals.