ApplicationNo. 06/014251 filed on 02/22/1979
US Classes:365/185.08, With volatile signal storage device257/316, With additional contacted control electrode257/369, Complementary insulated gate field effect transistors257/E27.062, Complementary MIS (EPO)257/E27.103, Electrically programmable ROM (EPO)365/181, Complementary conductivity365/185.1, Extended floating gate365/185.27, Substrate bias365/185.29, Erase365/185.32, Radiation erasure365/218Erase
ExaminersPrimary: Hecker, Stuart N.
Attorney, Agent or Firm
International ClassesG11C 16/04 (20060101)
H01L 27/092 (20060101)
H01L 27/115 (20060101)
H01L 27/085 (20060101)
Foreign Application Priority Data1978-02-22 CH
AbstractAn electrically reprogrammable non-volatile memory device is disclosed which includes complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n- -type substrate. The device comprises three main parts. The first part, which is used for writing, comprises a p-channel writing transistor, a p-channel control transistor and a resistance element. The second part, which comprises a second gate electrode capacitance coupled with the floating gate, is used for erasing. The third part is used for performing information read-out and consists of a p-channel transistor the gate of which forms a portion of the floating gate and the drain of which is connected to a read-out terminal and to the terminal of a loading element having its other terminal connected to a negative supply potential. This device enables writing control to be performed using a logical signal of the order of one volt, read-out being also performed with a low voltage value, with low energy consumption. Erasure of information can be performed electrically and the retention time is of several years.