U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etching

Patent 4209349 Issued on June 24, 1980. Estimated Expiration Date: Icon_subject November 3, 1998. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

3799777

Dielectrically isolated semiconductor devices
Patent #: 3966577
Issued on: 06/29/1976
Inventor: Hochberg

Process for fabricating narrow polycrystalline silicon members
Patent #: 4026740
Issued on: 05/31/1977
Inventor: Owen, III

Methods for making transistor structures
Patent #: 4037307
Issued on: 07/26/1977
Inventor: Smith

Selective oxidation method
Patent #: 4042726
Issued on: 08/16/1977
Inventor: Kaji ,   et al.

Edge etch method for producing narrow openings to the surface of materials
Patent #: 4063992
Issued on: 12/20/1977
Inventor: Hosack

Insulated-gate field-effect transistor with self-aligned contact hole to source or drain
Patent #: 4103415
Issued on: 08/01/1978
Inventor: Hayes

Methods of manufacturing semiconductor devices
Patent #: 4124933
Issued on: 11/14/1978
Inventor: Nicholas

Reactive ion etching method for producing deep dielectric isolation in silicon
Patent #: 4139442
Issued on: 02/13/1979
Inventor: Bondur ,   et al.

High performance bipolar device and method for making same Patent #: 4160991
Issued on: 07/10/1979
Inventor: Anantha ,   et al.

Inventors

Application

No. 05/957605 filed on 11/03/1978

US Classes:

438/305, Plural doping steps204/192.32, Sputter etching257/465, Geometric configuration of junction (e.g., fingers)257/E21.038, Characterized by process involved to create mask, e.g., lift-off mask, sidewalls, or to modify mask, such as pre-treatment, post-treatment (EPO)257/E21.252, By dry-etching (EPO)257/E21.556, Introducing electrical inactive or active impurities in local oxidation region, e.g., to alter LOCOS oxide growth characteristics or for additional isolation purpose (EPO)257/E29.054, Doping structure being parallel to channel length (EPO)438/306, Plural doping steps438/947Subphotolithographic processing

Examiners

Primary: Rutledge, L. Dewayne
Assistant: Saba, W. G.

Attorney, Agent or Firm

International Classes

H01L 21/762 (20060101)
H01L 21/70 (20060101)
H01L 21/033 (20060101)
H01L 29/02 (20060101)
H01L 21/311 (20060101)
H01L 21/02 (20060101)
H01L 29/10 (20060101)

Abstract

A method for forming a narrow, such as a submicrometer, dimensioned mask opening on a silicon body involving forming a first insulator region having substantially a horizontal surface and a substantially vertical surface. A second insulator is applied on both the horizontal surface and substantially vertical surfaces. The second insulator is composed of a material different from that of the first insulator layer. Reactive ion etching of the second layer removes the horizontal layer and provides a narrow dimensioned second insulator region on the silicon body. The surface of the silicon body is then thermally oxidized. The narrow dimensioned second insulator region is removed to form a narrow dimensioned mask opening.

Other References

  • Critchlow, D. L., "High Speed Mosfet . . . Advanced Lithography" Computer, vol. 9, No. 2, Feb. 1976, pp. 31-37
  • Pogge, H. B., "Narrow Line Widths Masking Method" I.B.M. Tech. Discl. Bull., Nov. 1976, vol. 19, No. 6
  • Abbas et al., "Extending Minimal Dimensions . . . Fabrication Processing" I.B.M. Tech. Discl. Bull., vol. 20, No. 4, Sep. 1977, pp. 1376-1378
  • Bersin, R. L., "Survey of Plasma-Etching Processes" Solid State Tech., May 1976, pp. 31-36
  • Jambotkar, C. G., "Method for Reducing Emitter-Base Contact . . . " I.B.M. Tech. Discl. Bull., vol. 19, No. 12, May 1977, pp. 4601-4604
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