Semiconductor device insulation method
Patent 4143456 Issued on March 13, 1979. Estimated Expiration Date: 
June 20, 1997. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 20, 1997. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3381071 3622419 3778686 Narrow lead contact for automatic face down bonding of electronic chips Patent #: 3938177 InventorAssigneeApplicationNo. 05/808216 filed on 06/20/1977US Classes:29/841, With encapsulating, e.g., potting, etc.174/521, Encapsulated (potted, molded, plastic filled)174/564, Seal257/687, Housing or package filled with solid or liquid electrically insulating material257/787, ENCAPSULATED257/E21.502, Encapsulation, e.g., encapsulation layer, coating (EPO)257/E21.503, Encapsulation of active face of flip chip device, e.g., under filling or under encapsulation of flip-chip, encapsulation perform on chip or mounting substrate (EPO)257/E21.512, Right-up bonding (EPO)257/E23.125, Substrate forming part of encapsulation (EPO)438/126And encapsulatingExaminersPrimary: James, Andrew J.Attorney, Agent or FirmInternational ClassesH01L 21/60 (20060101)H01L 23/31 (20060101) H01L 21/02 (20060101) H01L 23/28 (20060101) H01L 21/56 (20060101) Foreign Application Priority Data1976-06-28 JPAbstractA method for applying a protective covering for a semi-conductor device which comprises a circuit board having formed thereon a conductive pattern on which a chip of the semi-conductor device is mounted and electrically connected to said conductive pattern, an insulating resin film having a low surface energy to provide a repellent property and formed on said circuit board around the chip of the semi-conductor device by a printing technique, and a resin molded seal formed on said circuit board to conseal said chip within a space defined by said insulating resin film, the flow of resin being blocked by the repellent property of said insulating resin film during a molding process. | |
