High speed binary and binary coded decimal adder
Patent 4138731 Issued on February 6, 1979. Estimated Expiration Date: 
December 9, 1997. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
December 9, 1997. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3711693 3805045 3925651 Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results Patent #: 3991307 InventorsAssigneeApplicationNo. 05/859184 filed on 12/09/1977US Classes:708/685, Parallel708/683Coded decimalExaminersPrimary: Malzahn, David H.Attorney, Agent or FirmInternational ClassesG06F 7/48 (20060101)G06F 7/50 (20060101) Foreign Application Priority Data1976-12-30 JPAbstractA high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a binary coded decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and binary coded decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages. | |
