Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results Patent #: 3991307
ApplicationNo. 05/859184 filed on 12/09/1977
US Classes:708/685, Parallel708/683Coded decimal
ExaminersPrimary: Malzahn, David H.
Attorney, Agent or Firm
International ClassesG06F 7/48 (20060101)
G06F 7/50 (20060101)
Foreign Application Priority Data1976-12-30 JP
AbstractA high speed binary and binary coded decimal adder which employs a plurality of partial adders and a carry look ahead circuit and is adapted to effect a binary coded decimal addition with only one processing of the adder. The partial adders are each composed of a half adder for generating a bit generate signal and a bit propagate signal, a binary mode carry look ahead input signal generator circuit part, a binary coded decimal mode carry look ahead input signal generator circuit part, an intermediate adder part and a full adder part. The high speed binary and binary coded decimal adder is capable of providing the result of an addition at a speed corresponding to six to seven logical stages.