ApplicationNo. 05/790815 filed on 04/25/1977
US Classes:365/189.04, Simultaneous operations (e.g., read/write)365/230.03Plural blocks or banks
ExaminersPrimary: Hecker, Stuart N.
Attorney, Agent or Firm
International ClassesG11C 11/4097 (20060101)
G11C 16/04 (20060101)
G11C 16/10 (20060101)
G11C 11/34 (20060101)
G11C 8/04 (20060101)
G11C 11/409 (20060101)
G11C 16/06 (20060101)
G11C 17/14 (20060101)
Foreign Application Priority Data1976-04-26 JP
AbstractA latch circuit is provided on the input side of write-in circuit of a semiconductor memory device which is so formed that a common data line is used for data writing-in and data reading-out. Write-in data read serially into the latch circuit in a word unit is temporarily stored and held, so that the data is written simultaneously into various memory cells for in column units of the memory array.